// ******************************************************************************
// Copyright     :  Copyright (C) 2020, Hisilicon Technologies Co. Ltd.
// File name     :  pqm_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2020/3/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2020/03/24 21:57:27 Create file
// ******************************************************************************

#ifndef PQM_REG_OFFSET_H
#define PQM_REG_OFFSET_H

/* PQM_TOP Base address of Module's Register */
#define CSR_PQM_TOP_BASE (0xC000)

/* **************************************************************************** */
/*                      PQM_TOP Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_PQM_TOP_PQM_EDITION_REG (CSR_PQM_TOP_BASE + 0x0)           /* Version Register */
#define CSR_PQM_TOP_PQM_INITCTAB_START_REG (CSR_PQM_TOP_BASE + 0x4)    /* 配置表初始化使能寄存器 */
#define CSR_PQM_TOP_PQM_INITCTAB_DONE_REG (CSR_PQM_TOP_BASE + 0x8)     /* 配置表初始化状态寄存器 */
#define CSR_PQM_TOP_PQM_CFG_OK_REG (CSR_PQM_TOP_BASE + 0xC)            /* PQM 配置完成寄存器 */
#define CSR_PQM_TOP_PQM_INITLOGIC_DONE_REG (CSR_PQM_TOP_BASE + 0x10)   /* 芯片逻辑初始化状态寄存器 */
#define CSR_PQM_TOP_MEM_ECC_BYPASS_EN_REG (CSR_PQM_TOP_BASE + 0x14)    /* RAM ECC BYPASS控制寄存器 */
#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG0_REG (CSR_PQM_TOP_BASE + 0x18)    /* RAM CTRL_BUS寄存器0 */
#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG1_REG (CSR_PQM_TOP_BASE + 0x1C)    /* RAM CTRL_BUS寄存器1 */
#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG2_REG (CSR_PQM_TOP_BASE + 0x20)    /* RAM CTRL_BUS寄存器2 */
#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG3_REG (CSR_PQM_TOP_BASE + 0x24)    /* RAM CTRL_BUS寄存器3 */
#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG4_REG (CSR_PQM_TOP_BASE + 0x28)    /* RAM CTRL_BUS寄存器4 */
#define CSR_PQM_TOP_PQM_INT_VECTOR_REG (CSR_PQM_TOP_BASE + 0x100)      /* PQM Interrupt Vector  Register */
#define CSR_PQM_TOP_PQM_INT_REG (CSR_PQM_TOP_BASE + 0x104)             /* PQM Interrupt Register */
#define CSR_PQM_TOP_PQM_INT_EN_REG (CSR_PQM_TOP_BASE + 0x108)          /* PQM Interrupt Mask Register */
#define CSR_PQM_TOP_PQM_MEM_ERR_REQ0_REG (CSR_PQM_TOP_BASE + 0x10C)    /* PQM mem Error Request register0. */
#define CSR_PQM_TOP_PQM_MEM_ERR_REQ1_REG (CSR_PQM_TOP_BASE + 0x110)    /* PQM mem Error Request register1. */
#define CSR_PQM_TOP_PQM_MEM_ERR_REQ2_REG (CSR_PQM_TOP_BASE + 0x114)    /* PQM mem Error Request register2. */
#define CSR_PQM_TOP_PQM_MEM_ERR_REQ3_REG (CSR_PQM_TOP_BASE + 0x118)    /* PQM mem Error Request register3. */
#define CSR_PQM_TOP_PQM_ECC_ONE_BIT_INT_REG (CSR_PQM_TOP_BASE + 0x11C) /* RAM ECC ONE BIT ERROR */
#define CSR_PQM_TOP_PQM_ECC_TWO_BIT_INT_REG (CSR_PQM_TOP_BASE + 0x120) /* RAM ECC TWO BITS ERROR */
#define CSR_PQM_TOP_PQM_MQ_BIND_INT_REG (CSR_PQM_TOP_BASE + 0x130)     /* MQ MAPPING CONFIG ERROR */
#define CSR_PQM_TOP_PQM_MQ_BIND_MCD_INT_REG (CSR_PQM_TOP_BASE + 0x134) /* MQ MAPPING CONFIG FOR MCD ERROR */
#define CSR_PQM_TOP_PQM_FIFO_INT0_REG (CSR_PQM_TOP_BASE + 0x138) /* FIFO 0 interrupt,include write int and read int */
#define CSR_PQM_TOP_PQM_FIFO_INT0_MASK_REG \
    (CSR_PQM_TOP_BASE + 0x13C) /* FIFO 0 interrupt,include write int and read init mask */
#define CSR_PQM_TOP_PQM_FIFO_INT1_REG (CSR_PQM_TOP_BASE + 0x140) /* FIFO 1 interrupt,include write int and read int */
#define CSR_PQM_TOP_PQM_FIFO_INT1_MASK_REG \
    (CSR_PQM_TOP_BASE + 0x144) /* FIFO 1 interrupt,include write int and read init mask */
#define CSR_PQM_TOP_PQM_FIFO_INT2_REG (CSR_PQM_TOP_BASE + 0x148) /* FIFO 2 interrupt,include write int and read int */
#define CSR_PQM_TOP_PQM_FIFO_INT2_MASK_REG \
    (CSR_PQM_TOP_BASE + 0x14C) /* FIFO 2 interrupt,include write int and read init mask */
#define CSR_PQM_TOP_PQM_FIFO_INT3_REG (CSR_PQM_TOP_BASE + 0x150) /* FIFO 3 interrupt,include write int and read int */
#define CSR_PQM_TOP_PQM_FIFO_INT3_MASK_REG \
    (CSR_PQM_TOP_BASE + 0x154) /* FIFO 3 interrupt,include write int and read init mask */
#define CSR_PQM_TOP_PQM_FIFO_INT4_REG (CSR_PQM_TOP_BASE + 0x158) /* FIFO 4 interrupt,include write int and read int */
#define CSR_PQM_TOP_PQM_FIFO_INT4_MASK_REG \
    (CSR_PQM_TOP_BASE + 0x15C) /* FIFO 4 interrupt,include write int and read init mask */
#define CSR_PQM_TOP_PQM_FIFO_INT5_REG (CSR_PQM_TOP_BASE + 0x160) /* FIFO 5 interrupt,include write int and read int */
#define CSR_PQM_TOP_PQM_FIFO_INT5_MASK_REG \
    (CSR_PQM_TOP_BASE + 0x164) /* FIFO 5 interrupt,include write int and read init mask */
#define CSR_PQM_TOP_PQM_RX_RING_E0_ERR_INT_REG (CSR_PQM_TOP_BASE + 0x168) /* Receive Ring E0 error int */
#define CSR_PQM_TOP_PQM_RX_RING_E1_ERR_INT_REG (CSR_PQM_TOP_BASE + 0x16C) /* Receive Ring E0 error int */
#define CSR_PQM_TOP_PQM_FIFO_ST0_REG (CSR_PQM_TOP_BASE + 0x180)           /* fifo full and empt state0 */
#define CSR_PQM_TOP_PQM_FIFO_ST1_REG (CSR_PQM_TOP_BASE + 0x184)           /* fifo full and empt state1 */
#define CSR_PQM_TOP_PQM_FIFO_ST2_REG (CSR_PQM_TOP_BASE + 0x188)           /* fifo full and empt state2 */
#define CSR_PQM_TOP_PQM_RW_RSV0_REG (CSR_PQM_TOP_BASE + 0x300)            /* PQM reserved rw register. */
#define CSR_PQM_TOP_PQM_RW_RSV1_REG (CSR_PQM_TOP_BASE + 0x304)            /* PQM reserved rw register. */
#define CSR_PQM_TOP_PQM_RW_RSV2_REG (CSR_PQM_TOP_BASE + 0x308)            /* PQM reserved rw register. */
#define CSR_PQM_TOP_PQM_RW_RSV3_REG (CSR_PQM_TOP_BASE + 0x30C)            /* PQM reserved rw register. */
#define CSR_PQM_TOP_PQM_INDRECT_CTRL_REG (CSR_PQM_TOP_BASE + 0x310)       /* Indirect access ctrl Register。 */
#define CSR_PQM_TOP_PQM_INDRECT_TIMEOUT_REG (CSR_PQM_TOP_BASE + 0x314)    /* Indirect Access Timeout Register。 */
#define CSR_PQM_TOP_PQM_INDRECT_DATA_0_REG (CSR_PQM_TOP_BASE + 0x318)     /* Indirect Access Data Register BIT63_32 */
#define CSR_PQM_TOP_PQM_INDRECT_DATA_1_REG (CSR_PQM_TOP_BASE + 0x31C)     /* Indirect Access Data Register BIT31_0 */
#define CSR_PQM_TOP_PQM_PASS_THROUGH_CFG_REG (CSR_PQM_TOP_BASE + 0x320)   /* Pass through function enable register. */
#define CSR_PQM_TOP_PQM_WEIGHT_OFFSET_REG (CSR_PQM_TOP_BASE + 0x324)      /* Normal queue weight offset */
#define CSR_PQM_TOP_PQM_PPS_SHAPER_CFG_PKTLEN_REG (CSR_PQM_TOP_BASE + 0x328) /* PQM Shaper Config Pktlen */
#define CSR_PQM_TOP_PQM_ROOT_SCH_WEIGHT_CFG_REG (CSR_PQM_TOP_BASE + 0x32C)   /* PQM ROOT SCH WEIGHT Config */
#define CSR_PQM_TOP_HOST_WEIGHT_0_REG (CSR_PQM_TOP_BASE + 0x340)             /* Normal MQ host weight */
#define CSR_PQM_TOP_HOST_WEIGHT_1_REG (CSR_PQM_TOP_BASE + 0x344)             /* Normal MQ host weight */
#define CSR_PQM_TOP_HOST_WEIGHT_2_REG (CSR_PQM_TOP_BASE + 0x348)             /* Normal MQ host weight */
#define CSR_PQM_TOP_HOST_WEIGHT_3_REG (CSR_PQM_TOP_BASE + 0x34C)             /* Normal MQ host weight */
#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x350) /* HOST Node Shaper BPS Configuration Table */
#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x354) /* HOST Node Shaper BPS Configuration Table */
#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x358) /* HOST Node Shaper BPS Configuration Table */
#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x35C) /* HOST Node Shaper BPS Configuration Table */
#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x360) /* HOST Node Shaper PPS_Configuration Table */
#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x364) /* HOST Node Shaper PPS_Configuration Table */
#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x368) /* HOST Node Shaper PPS_Configuration Table */
#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x36C) /* HOST Node Shaper PPS_Configuration Table */
#define CSR_PQM_TOP_EP_WEIGHT_0_REG (CSR_PQM_TOP_BASE + 0x370)         /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_1_REG (CSR_PQM_TOP_BASE + 0x374)         /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_2_REG (CSR_PQM_TOP_BASE + 0x378)         /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_3_REG (CSR_PQM_TOP_BASE + 0x37C)         /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_4_REG (CSR_PQM_TOP_BASE + 0x380)         /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_5_REG (CSR_PQM_TOP_BASE + 0x384)         /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_6_REG (CSR_PQM_TOP_BASE + 0x388)         /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_7_REG (CSR_PQM_TOP_BASE + 0x38C)         /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_8_REG (CSR_PQM_TOP_BASE + 0x390)         /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_9_REG (CSR_PQM_TOP_BASE + 0x394)         /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_10_REG (CSR_PQM_TOP_BASE + 0x398)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_11_REG (CSR_PQM_TOP_BASE + 0x39C)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_12_REG (CSR_PQM_TOP_BASE + 0x3A0)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_13_REG (CSR_PQM_TOP_BASE + 0x3A4)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_14_REG (CSR_PQM_TOP_BASE + 0x3A8)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_15_REG (CSR_PQM_TOP_BASE + 0x3AC)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_16_REG (CSR_PQM_TOP_BASE + 0x3B0)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_17_REG (CSR_PQM_TOP_BASE + 0x3B4)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_18_REG (CSR_PQM_TOP_BASE + 0x3B8)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_19_REG (CSR_PQM_TOP_BASE + 0x3BC)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_20_REG (CSR_PQM_TOP_BASE + 0x3C0)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_21_REG (CSR_PQM_TOP_BASE + 0x3C4)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_22_REG (CSR_PQM_TOP_BASE + 0x3C8)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_23_REG (CSR_PQM_TOP_BASE + 0x3CC)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_24_REG (CSR_PQM_TOP_BASE + 0x3D0)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_25_REG (CSR_PQM_TOP_BASE + 0x3D4)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_26_REG (CSR_PQM_TOP_BASE + 0x3D8)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_27_REG (CSR_PQM_TOP_BASE + 0x3DC)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_28_REG (CSR_PQM_TOP_BASE + 0x3E0)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_29_REG (CSR_PQM_TOP_BASE + 0x3E4)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_30_REG (CSR_PQM_TOP_BASE + 0x3E8)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_WEIGHT_31_REG (CSR_PQM_TOP_BASE + 0x3EC)        /* Normal MQ EP Node weight */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x3F0) /* EP Node Shaper BPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x3F4) /* EP Node Shaper BPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x3F8) /* EP Node Shaper BPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x3FC) /* EP Node Shaper BPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_4_REG (CSR_PQM_TOP_BASE + 0x400) /* EP Node Shaper BPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_5_REG (CSR_PQM_TOP_BASE + 0x404) /* EP Node Shaper BPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_6_REG (CSR_PQM_TOP_BASE + 0x408) /* EP Node Shaper BPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_7_REG (CSR_PQM_TOP_BASE + 0x40C) /* EP Node Shaper BPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_8_REG (CSR_PQM_TOP_BASE + 0x410) /* EP Node Shaper BPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_9_REG (CSR_PQM_TOP_BASE + 0x414) /* EP Node Shaper BPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_10_REG \
    (CSR_PQM_TOP_BASE + 0x418) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_11_REG \
    (CSR_PQM_TOP_BASE + 0x41C) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_12_REG \
    (CSR_PQM_TOP_BASE + 0x420) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_13_REG \
    (CSR_PQM_TOP_BASE + 0x424) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_14_REG \
    (CSR_PQM_TOP_BASE + 0x428) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_15_REG \
    (CSR_PQM_TOP_BASE + 0x42C) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_16_REG \
    (CSR_PQM_TOP_BASE + 0x430) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_17_REG \
    (CSR_PQM_TOP_BASE + 0x434) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_18_REG \
    (CSR_PQM_TOP_BASE + 0x438) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_19_REG \
    (CSR_PQM_TOP_BASE + 0x43C) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_20_REG \
    (CSR_PQM_TOP_BASE + 0x440) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_21_REG \
    (CSR_PQM_TOP_BASE + 0x444) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_22_REG \
    (CSR_PQM_TOP_BASE + 0x448) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_23_REG \
    (CSR_PQM_TOP_BASE + 0x44C) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_24_REG \
    (CSR_PQM_TOP_BASE + 0x450) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_25_REG \
    (CSR_PQM_TOP_BASE + 0x454) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_26_REG \
    (CSR_PQM_TOP_BASE + 0x458) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_27_REG \
    (CSR_PQM_TOP_BASE + 0x45C) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_28_REG \
    (CSR_PQM_TOP_BASE + 0x460) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_29_REG \
    (CSR_PQM_TOP_BASE + 0x464) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_30_REG \
    (CSR_PQM_TOP_BASE + 0x468) /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_31_REG \
    (CSR_PQM_TOP_BASE + 0x46C)                                       /* EP Node Shaper BPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x470) /* EP Node Shaper PPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x474) /* EP Node Shaper PPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x478) /* EP Node Shaper PPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x47C) /* EP Node Shaper PPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_4_REG (CSR_PQM_TOP_BASE + 0x480) /* EP Node Shaper PPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_5_REG (CSR_PQM_TOP_BASE + 0x484) /* EP Node Shaper PPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_6_REG (CSR_PQM_TOP_BASE + 0x488) /* EP Node Shaper PPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_7_REG (CSR_PQM_TOP_BASE + 0x48C) /* EP Node Shaper PPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_8_REG (CSR_PQM_TOP_BASE + 0x490) /* EP Node Shaper PPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_9_REG (CSR_PQM_TOP_BASE + 0x494) /* EP Node Shaper PPS Configuration Table for NS \
                                                                      */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_10_REG \
    (CSR_PQM_TOP_BASE + 0x498) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_11_REG \
    (CSR_PQM_TOP_BASE + 0x49C) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_12_REG \
    (CSR_PQM_TOP_BASE + 0x4A0) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_13_REG \
    (CSR_PQM_TOP_BASE + 0x4A4) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_14_REG \
    (CSR_PQM_TOP_BASE + 0x4A8) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_15_REG \
    (CSR_PQM_TOP_BASE + 0x4AC) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_16_REG \
    (CSR_PQM_TOP_BASE + 0x4B0) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_17_REG \
    (CSR_PQM_TOP_BASE + 0x4B4) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_18_REG \
    (CSR_PQM_TOP_BASE + 0x4B8) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_19_REG \
    (CSR_PQM_TOP_BASE + 0x4BC) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_20_REG \
    (CSR_PQM_TOP_BASE + 0x4C0) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_21_REG \
    (CSR_PQM_TOP_BASE + 0x4C4) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_22_REG \
    (CSR_PQM_TOP_BASE + 0x4C8) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_23_REG \
    (CSR_PQM_TOP_BASE + 0x4CC) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_24_REG \
    (CSR_PQM_TOP_BASE + 0x4D0) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_25_REG \
    (CSR_PQM_TOP_BASE + 0x4D4) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_26_REG \
    (CSR_PQM_TOP_BASE + 0x4D8) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_27_REG \
    (CSR_PQM_TOP_BASE + 0x4DC) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_28_REG \
    (CSR_PQM_TOP_BASE + 0x4E0) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_29_REG \
    (CSR_PQM_TOP_BASE + 0x4E4) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_30_REG \
    (CSR_PQM_TOP_BASE + 0x4E8) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_31_REG \
    (CSR_PQM_TOP_BASE + 0x4EC) /* EP Node Shaper PPS Configuration Table for NS */
#define CSR_PQM_TOP_PQM_SHAP_BYPASS_CFG_REG (CSR_PQM_TOP_BASE + 0x4F0)  /* PQM Shaper Bypass Configuration */
#define CSR_PQM_TOP_PQM_HOST_EP_XON_CFG_REG (CSR_PQM_TOP_BASE + 0x1000) /* The XON Configuration of the HOST EP node \
                                                                         */
#define CSR_PQM_TOP_PQM_HOST_XON_CFG_REG (CSR_PQM_TOP_BASE + 0x1004)    /* The XON Configuration of the HOST node */
#define CSR_PQM_TOP_PQM_HOST_EP_BPS_SPF_ST_REG \
    (CSR_PQM_TOP_BASE + 0x1008) /* The BPS Shap Pass Flag State of the HOST EP node */
#define CSR_PQM_TOP_PQM_HOST_EP_PPS_SPF_ST_REG \
    (CSR_PQM_TOP_BASE + 0x100C) /* The PPS Shap Pass Flag State of the HOST EP node */
#define CSR_PQM_TOP_PQM_HOST_SPF_ST_REG (CSR_PQM_TOP_BASE + 0x1010)   /* The Shap Pass Flag State of the HOST node */
#define CSR_PQM_TOP_PQM_SCH_BP_STA_REG (CSR_PQM_TOP_BASE + 0x1014)    /* PQM ROOT Level backpress status Register */
#define CSR_PQM_TOP_PQM_SCH_EP_BP_STA_REG (CSR_PQM_TOP_BASE + 0x1018) /* PQM HSOT_EP Level backpress status Register \
                                                                       */
#define CSR_PQM_TOP_PQM_FIFO_TH_CFG_REG (CSR_PQM_TOP_BASE + 0x101C)   /* The Threshold Config Of PQM FIFO */
#define CSR_PQM_TOP_PQM_DPL_INFO_PTR0_REG (CSR_PQM_TOP_BASE + 0x1020) /* PQM DPL INFO 0 status Register */
#define CSR_PQM_TOP_PQM_DPL_INFO_PTR1_REG (CSR_PQM_TOP_BASE + 0x1024) /* PQM DPL INFO 1 status Register */
#define CSR_PQM_TOP_PQM_MCD_DU_INFO_PTR0_REG (CSR_PQM_TOP_BASE + 0x1028)    /* PQM MCD DU INFO 0  status Register */
#define CSR_PQM_TOP_PQM_MCD_DU_INFO_PTR1_REG (CSR_PQM_TOP_BASE + 0x102C)    /* PQM MCD DU INFO  1 status Register */
#define CSR_PQM_TOP_PQM_UNCRT_ERR_MASK_REG (CSR_PQM_TOP_BASE + 0x1400)      /* PQM Urgency Interrupt Mask Register。 */
#define CSR_PQM_TOP_PQM_UNCRT_ERR_CLR_REG (CSR_PQM_TOP_BASE + 0x1404)       /* PQM Urgency Interrupt Clear Register。 */
#define CSR_PQM_TOP_PQ_EQS_CNT_REG (CSR_PQM_TOP_BASE + 0x1408)              /* PQM MQ ENQ EQS count */
#define CSR_PQM_TOP_PQ_DQS_CNT_REG (CSR_PQM_TOP_BASE + 0x140C)              /* PQM MQ DQS count */
#define CSR_PQM_TOP_PQ_EMPT_DQS_CNT_REG (CSR_PQM_TOP_BASE + 0x1410)         /* PQM MQ EMPT DQS count */
#define CSR_PQM_TOP_PQ_SCH_DQR_CNT_REG (CSR_PQM_TOP_BASE + 0x1414)          /* PQM MQ SCH DQR count */
#define CSR_PQM_TOP_PQ_SCH_EMPT_DQR_CNT_REG (CSR_PQM_TOP_BASE + 0x1418)     /* PQM MQ SCH EMPT DQR count */
#define CSR_PQM_TOP_PQ_PT_DQR_CNT_REG (CSR_PQM_TOP_BASE + 0x141C)           /* PQM MQ PT DQR count */
#define CSR_PQM_TOP_PQ_DPL_CNT_REG (CSR_PQM_TOP_BASE + 0x1420)              /* PQM MQ DPL count */
#define CSR_PQM_TOP_PQ_DU_VLD_CNT_REG (CSR_PQM_TOP_BASE + 0x1424)           /* PQM DU VLD count */
#define CSR_PQM_TOP_PQ_DU_ERR_CNT_REG (CSR_PQM_TOP_BASE + 0x1428)           /* PQM DU ERR count */
#define CSR_PQM_TOP_PQM_ECC_1BIT_ERR_CNT_REG (CSR_PQM_TOP_BASE + 0x142C)    /* PQM MEMORY ECC 1BIT ERR count */
#define CSR_PQM_TOP_PQM_ECC_2BIT_ERR_CNT_REG (CSR_PQM_TOP_BASE + 0x1430)    /* PQM MEMORY ECC 2BIT ERR count */
#define CSR_PQM_TOP_SCH_PQ_DFX_CFG_REG (CSR_PQM_TOP_BASE + 0x14A0)          /* PQ DFX NUM configure */
#define CSR_PQM_TOP_SCH_PQ_DFX_UP_CNT_REG (CSR_PQM_TOP_BASE + 0x14A4)       /* PQ DFX NUM  ENQ UP count */
#define CSR_PQM_TOP_SCH_PQ_DFX_EMPT_UP_CNT_REG (CSR_PQM_TOP_BASE + 0x14A8)  /* PQ DFX NUM  ENQ EMPT UP count */
#define CSR_PQM_TOP_SCH_PQ_DFX_SCH_CNT_REG (CSR_PQM_TOP_BASE + 0x14AC)      /* PQ DFX NUM  DEQ SCH count */
#define CSR_PQM_TOP_SCH_PQ_DFX_PT_DEQ_CNT_REG (CSR_PQM_TOP_BASE + 0x14B0)   /* PQ DFX NUM  PT DEQ SCH count */
#define CSR_PQM_TOP_SCH_PQ_DFX_EMPT_SCH_CNT_REG (CSR_PQM_TOP_BASE + 0x14B4) /* PQ DFX NUM  DEQ EMPT SCH count */
#define CSR_PQM_TOP_SCH_PQ_DFX_DU_CNT_REG (CSR_PQM_TOP_BASE + 0x14B8)       /* PQ DFX NUM  DU count */

#endif // PQM_REG_OFFSET_H
